Level for award<br> (Hons, MSc, <br> PhD)?
Abstract content <br> (Max 300 words)<br><a href="http://events.saip.org.za/getFile.py/access?resId=0&materialId=0&confId=34" target="_blank">Formatting &<br>Special chars</a>
Big Science projects such as the ATLAS experiment at the Large Hadron Collider at CERN require huge amounts of data to be transferred and processed. General purpose cluster computers are not suitable for the data throughput that is required, instead customised computer systems need to be designed and implemented. This project aims to design and build an Ethernet to PCI Express (PCIe) bridge/ packet manager for such a computer system. This board will be created using a Zynq fully programmable System on Chip (Soc) that uses both an FPGA and an ARM processor on a single chip. For initial prototyping a Zedboard Development kit will be used.
This board will be in direct communication with a small cluster of ARM processors nodes through a PCIe backplane. Its roll will be to take in data through high speed Ethernet, modify it for PCIe transport and send it to an available ARM node. Once data is processed by a node it can be send back to the Zynq board for Ethernet transport. This project will be part of the electronics upgrade of the Tile Calorimeter. Later designs will have the entire ARM cluster and bridge on a single mezzanine card that can be attached to the Super Read Out Driver (sROD) of the Tile Calorimeter. It will assist with the processing and formatting of the massive amounts of data being received from the detector.
Main supervisor (name and email)<br>and his / her institution
Bruce Mellado Garcia, Bruce.Mellado.Garcia@cern.ch , The university of the Witwatersrand
Apply to be<br> considered for a student <br> award (Yes / No)?
Would you like to <br> submit a short paper <br> for the Conference <br> Proceedings (Yes / No)?