7-11 July 2014
Africa/Johannesburg timezone
<a href="http://events.saip.org.za/internalPage.py?pageId=16&confId=34"><font color=#0000ff>SAIP2014 Proceedings published on 17 April 2015</font></a>

The development of a general purpose Processing Unit for the upgraded electronics of the ATLAS detector Tile Calorimeter

8 Jul 2014, 14:00
D Les 101

D Les 101

Oral Presentation Track B - Nuclear, Particle and Radiation Physics NPRP


Mr Mitchell Cox (University of the Witwatersrand)

Apply to be<br> considered for a student <br> &nbsp; award (Yes / No)?


Main supervisor (name and email)<br>and his / her institution

Bruce Mellado, Wits, bruce.mellado@wits.ac.za

Level for award<br>&nbsp;(Hons, MSc, <br> &nbsp; PhD)?


Abstract content <br> &nbsp; (Max 300 words)<br><a href="http://events.saip.org.za/getFile.py/access?resId=0&materialId=0&confId=34" target="_blank">Formatting &<br>Special chars</a>

Modern Big Science projects such as the Large Hadron Collider at CERN generate enormous amounts of raw data which presents a serious computing challenge. After planned upgrades in 2022, the data output from the ATLAS Tile Calorimeter will increase by 200 times to over 40 Tb/s! ARM processors are common in mobile devices due to their low cost, low energy consumption and high performance. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. This PU could be used for a variety of high-level functions on the high-throughput raw data such as spectral analysis and histograms to detect possible issues in the detector at a low level. High-throughput I/O interfaces are not typical in consumer ARM System on Chips but high data throughput capabilities of greater than 20 Gb/s per PU is feasible via the novel use of PCI-Express as the I/O interface to the ARM processors. An overview of the PU is given and the results for performance and throughput testing of Freescale Semiconductor i.MX6 quad-core ARM Cortex-A9 processors are presented.

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Primary author

Mr Mitchell Cox (University of the Witwatersrand)

Presentation Materials

Peer reviewing