Speaker
Dr
Hermann Uys
(National Laser Centre, CSIR)
Description
The design, fabrication and preliminary testing of a chipscale, multi-zone, surface
electrode ion trap is reported. The modular design and fabrication techniques used are anticipated to advance scalability of ion trap quantum computing architectures.
Primary author
Dr
Hermann Uys
(National Laser Centre, CSIR)
Co-authors
Dr
A.P. VanDevender
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
C Ospelkaus
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
D Leibfried
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
D.J. Wineland
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
J Britton
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
J.H. Wesenberg
(Centre for Quantum Technologies, National University of Singapore, Singapore)
Dr
J.J. Bollinger
(National Institute of Standards and Technology, Boulder, Colorado, USA)
Dr
J.M. Amini
(Georgia Tech Quantum Institute, GTRI/STL, Atlanta, Georgia, USA)
Dr
S Seidelin
(Institut Neel-CNRS, BP 166, 25, rue des Martyrs, 38042 Grenoble Cedex 9, France)
