Speaker
Apply to be<br> considered for a student <br> award (Yes / No)?
Yes
Main supervisor (name and email)<br>and his / her institution
Prof Ekow Otoo (ekow.otoo@wits.ac.za) and Bruce Mellado (bruce.mellado@wits.ac.za) - University Of the Witwatersrand
Level for award<br> (Hons, MSc, <br> PhD, N/A)?
PhD
Would you like to <br> submit a short paper <br> for the Conference <br> Proceedings (Yes / No)?
Yes
Please indicate whether<br>this abstract may be<br>published online<br>(Yes / No)
Yes
Abstract content <br> (Max 300 words)<br><a href="http://events.saip.org.za/getFile.py/access?resId=0&materialId=0&confId=34" target="_blank">Formatting &<br>Special chars</a>
The ATLAS detector, operated at the Large Hadron Collider (LHC) records proton-proton collisions at CERN every 50ns resulting in a sustained data flow up to Pb/s. Tile Calorimeter is a sub-component of the ATLAS detector in charge of measuring the energy, position and time of hadrons produced in proton-proton collisions. These physics quantities are generated at a rate of 40 MHz out of 10 thousand channels. The upgraded Tile Calorimeter of the ATLAS experiment will, sustain about 5PB/s of digital throughput. These massive data rates require extremely fast data capture and processing. Although there has been a steady increase in the processing speed of CPU/GPGPU assembled for high performance computing, the rate of data input and output, even under parallel I/O, has not kept up with the general increase in computing speeds. The problem then is whether one can implement an I/O subsystem infrastructure capable of meeting the computational speeds required by the upgraded LHC ATLAS TileCal.
We propose a technique that leverages the Partitioned Global Address Space (PGAS) model of computing to maintain an in-memory data-store for the Processing Unit (PU) of the upgraded electronics of the Tile Calorimeter for high throughput data processing. The approach seeks to enhance data processing throughput for the PU which will be used as a co-processor to offload some data processing tasks of the Super Rod (sROD) of the upgraded TileCal. The physical memory of the PUs are aggregated into a large global logical address space using RDMA-capable interconnects such as PCI-Express. The technique uses RDMA in user space for high throughput data processing.